FIRST Components provides thousands of model display modules, including TN/STN LCD, OLED, and TFT. And there are many types of interfaces to deliver image data to the display module. Customers may question which one is the best or can meet the requirement. This article will discuss an issue regarding the data transfer of display interfaces.
A significant issue with the display interface is Communication bandwidth (BW). Why is BW a matter? BW represents the measure of data transfer in the communication channel. So the BW affects display response to screen data, which means the display's refresh rate. The display performance, in other words.
Well-known display interfaces nowadays:
Display raw data sent via Data bus according to control bus signal. Communication bandwidth depends on enabling speed running on Driver IC. QVGA 320x240 dot matrix LCD i.e., the communication bandwidth will be 320 * 240 / 8 bit (data width) * 60 fps = 576KHz at ENABLE signal.
The RGB interface is to transmit the drive timing to the display driver IC through the data input/output in a parallel manner, including R/G/B data, vertical synchronization signal (V-SYNC, Vertical synchronizing signal), horizontal synchronization signal (H-SYNC), horizontal synchronizing signal), data enable (DE, Data Enable) signal, and clock signal PCLK (Pixel Clock). The display interface of RGB666 is as follows:
Display raw data transferred same as above. But the display resolution is getting higher and higher. i.e., WVGA 800 * 480 (pixels) * 60 fps = 23.04 MHz. (PCLK)
SPI is a master-slave-based interface, usually with a Master (master device) and one or multi slave (slave devices). There are 4 pins on the interface. The connection method and hardware structure are as follows:
SCLK: The synchronous clock used by all devices. The master drives this clock and the slaves receive the clock.
MOSI: Master out, slave in. This is the main data line driven by the master to all slaves on the SPI bus. Only the selected slave clocks data from MOSI.
MISO: Master in, slave out. This is the main data line driven by the selected slave to the master. Only the selected slave may drive this circuit. In fact, it is the only circuit in the SPI bus arrangement that a slave is ever permitted to drive.
CS: Chip Select. This signal is unique to each slave. When active the selected slave must drive MISO.
Display data transferred in sequential. Display interface communication bandwidth i.e., QVGA 320 * 240 (pixels) * 16 bit (color depth) * 30 fps = 36.864 MHz.
Different from the point-to-point (or point-to-multipoint) base of SPI, I²C is interfaced in the form of a data bus, which allows multiple master devices and multiple slave devices to be connected in series. The interface method and hardware structure are as follows:
Standard mode = 100K bit/s.
Full speed mode = 400K bit/s.
Fast mode = 1M bit/s.
High speed mode = 3.2M bit/s.
Display data transferred in RGB sequential. Display interface communication bandwidth i.e., QVGA 320 * 240 (pixels) * 3 dot * 30 fps = 6912000 Hz (DCLK).
LVDS is a technical standard introduced in 1994 that specifies electrical characteristics of a differential, serial signaling standard, but it is not a protocol. LVDS is a physical layer specification only; many data communication standards and applications use it and add a data link layer as defined in the OSI model on top of it. LVDS operates at low power and can run at very high speeds using inexpensive twisted-pair copper cables.
Early on, the notebook computer and LCD display vendors commonly used LVDS instead of FPD-Link when referring to their protocol. The term LVDS has mistakenly become synonymous with Flat Panel Display Link in the video-display engineering vocabulary.
MIPI Alliance aimed at reducing the cost of display controllers in mobile devices. It defines a serial bus and a communication protocol between the host, the source of the image data, and the destination device. It is the expected target at LCD and similar display technologies.
DSI specifies a high-speed (e.g., 4.5 Gbit/s/lane for D-PHY 2.0) differential signaling point-to-point serial bus. This bus includes one high-speed clock lane and one or more data lanes.
Image data on the bus is interleaved with horizontal and vertical blanking intervals signals. The data is transferred to the display in real-time and not stored by the device to save frame buffer memory in the display. However, it also means that the device must be continuously refreshed (at a rate such as 30 or 60 frames per second) or lose the image. Image data is only sent in HS mode. When in HS mode, commands are transmitted during the vertical blanking interval.
A LCD controller has been phased out, and the customer would like to have a pin-to-pin compatible module to replace it. RD owners had designed a PCB with an MCU for the compatible interface. The experimental results on ENABLE signal must be as long as 9.92uS at least. This means the maximum communication BW is around 100KBPS.
We can see a few defect points below when shortening ENABLE time as 9.84uS (the communication speed is up to 101KBPS).
Which interface is the best? There is no absolute answer to this question. The users should choose the suitable interface for their applications, not the best. Let's see the following comparison of the pros and cons of these interfaces.
|Display Interface||Resolution||Speed||Pin Count.||Noise||Power Consumption||Connect Distance||Cost|
|Serial RGB 6/8||Middle||Fast||Less||Worst||High||Short||Low|